Technical Field
This invention relates in general to electronics and, more particularly, to a digital phase locked loop.
Description of the Related Art
A great reduction of the transistor features in recently developed deep-submicron CMOS processes shifts the design paradigm towards more digitally-intensive techniques. In a monolithic implementation, the manufacturing cost of a design is measured not in terms of a number of devices used but rather in terms of the occupied silicon area, no matter what the actual circuit complexity.
Analog and RF circuits used in communication circuits, however, are not easily implemented in a deep-submicron CMOS process. For example, in Texas Instruments' CMOS process (CO35) of 0.08 □m L-effective features a digital gate density of 150 K equivalent (2-input NAND) gates per mm2. An average-size inductor for an integrated LC oscillator occupies about 0.5 mm2 of silicon area. A low-noise charge pump, or a low-distortion image-reject modulator, both good examples of classical RF transceiver components, occupy roughly about the same area, which could be traded for tens of thousands of digital gates.
Migrating to a digitally-intensive synthesizer architecture brings forth the following well-known advantages: (1) fast design turn-around cycle using automated CAD tools (VHDL or Verilog hardware-level description language, synthesis, auto-place and auto-route with timing-driven algorithms, parasitic backannotation and postlayout optimization), (2) much lower parameter variability than with analog circuits, (3) ease of testability, (4) lower silicon area and dissipated power that gets better with each CMOS technology advancement (also called a “process node”) and (5) excellent chances of first-time silicon success. Commercial analog circuits usually require several design iterations to meet marketing requirements.
There is a wide array of opportunities that integration presents. The most straightforward way would be to merge various digital sections into a single silicon die, such as DRAM or Flash memory embedded into DSP or controller. More difficult would be integrating the analog baseband with the digital baseband. Care must be taken here to avoid coupling of digital noise into the high-precision analog section. In addition, the low amount of voltage headroom challenges one to find new circuit and architecture solutions. Integrating the analog baseband into RF transceiver section presents a different set of challenges: the conventional Bi-CMOS RF process is tuned for high-speed operation with a number of available passive components and does not fundamentally stress high precision.
Sensible integration of diverse sections results in a number of advantages: (1) lower total silicon area—in a deep-submicron CMOS design, the silicon area is often bond-pad limited; consequently, it is beneficial to merge various functions on a single silicon die to maximize the core to bond-pad ratio, (2) lower component count and thus lower packaging cost, (3) power reduction—no need to drive large external inter-chip connections and (4) lower printed-circuit board (PCB) area, thus saving the precious “real estate.”
Deep-submicron CMOS processes present new integration opportunities on one hand, but make it extremely difficult to implement traditional analog circuits, on the other. One such problem involves the design of a digital phase locked loop (DPLL). A PLL loop is a fixed-point phase domain architecture whose purpose is to generate a stable RF signal at a desired frequency. The underlying frequency stability of the system is derived from a reference clock generated by a crystal oscillator, such as a temperature-compensated crystal oscillator (TCXO) used in mobile phones. Phase information between the output signal and the reference signal is used to update a controllable oscillator. This information is generated at an active edge of the reference clock. However, greater accuracy could be obtained by more frequent determinations of the phase information, leading to more frequent updates of the controllable oscillator.
Therefore, a need has arisen for a method and apparatus for a phase locked loop design that provides for increase accuracy in the output signal.